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LTC1448 Dual 12-Bit Rail-to-Rail Micropower DAC
FEATURES
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DESCRIPTION
The LTC(R)1448 is a dual rail-to-rail voltage output, 12-bit digital-to-analog converter (DAC). It includes rail-to-rail output buffer amplifiers and an easy-to-use 3-wire serial interface. It is available in 8-pin SO and PDIP packages and provides the smallest footprint of any dual 12-bit DAC. The LTC1448 has an external reference input pin (REF) and its outputs swing from 0V to REF. The REF input can be tied to VCC providing rail-to-rail operation from supplies of 2.7V to 5.5V. (For devices with internal reference see the LTC1446 data sheet.) The LTC1448 dissipates 2.5mW from a 5V supply. The low power supply current and the small SO-8 package make the LTC1448 ideal for battery-powered applications.
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SO-8 Package 12-Bit Resolution Buffered True Rail-to-Rail Voltage Output External Reference Input Can Be Tied to VCC Output Swings from 0V to VREF 3V and 5V Supply Operation Schmitt Trigger on Clock Input Allows Direct Optocoupler Interface Power-On Reset Clears DACs to 0V 3-Wire Serial Interface Maximum DNL Error: 0.5LSB Low Cost
APPLICATIONS
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Digital Calibration Industrial Process Control Automatic Test Equipment Cellular Telephones
, LTC and LT are registered trademarks of Linear Technology Corporation.
TYPICAL APPLICATION
Functional Block Diagram: 12-Bit Rail-to-Rail Dual DAC
2.7V TO 5.5V 0.5 7 VCC 2 DIN 4 REF
DNL ERROR (LSB)
+
12-BIT DAC B
VOUT B 8
P 1 CLK 3 CS/LD 24-BIT SHIFT REG AND DAC LATCH
-
RAIL-TO-RAIL VOLTAGE OUTPUTS
+
12-BIT DAC A
VOUT A 5
-
POWER-ON RESET GND 6
1448 TA01
U
U
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Differential Nonlinearity vs Input Code
0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1448 TA02
1
LTC1448 ABSOLUTE MAXIMUM RATINGS
VCC to GND .............................................. - 0.5V to 7.5V Logic Inputs to GND ................................ - 0.5V to 7.5V VOUT A, VOUT B, REF to GND ........... - 0.5V to VCC + 0.5V Maximum Junction Temperature .......................... 125C Operating Temperature Range LTC1448C ............................................ 0C to 70C LTC1448I......................................... - 40C to 85C Storage Temperature Range ................ - 65C to 150C Lead Temperature (Soldering, 10 sec)................. 300C
PACKAGE/ORDER I FOR ATIO
TOP VIEW CLK 1 DIN 2 CS/LD 3 REF 4 N8 PACKAGE 8-LEAD PDIP 8 7 6 5 VOUT B VCC GND VOUT A
ORDER PART NUMBER LTC1448CN8 LTC1448IN8 LTC1448CS8 LTC1448IS8 S8 PART MARKING 1448 1448I
S8 PACKAGE 8-LEAD PLASTIC SO
TJMAX = 125C, JA = 100C/W (N8) TJMAX = 125C, JA = 150C/W (S8)
Consult factory for Military grade parts.
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT A and VOUT B unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL DAC Resolution Monotonicity DNL INL VOS VOSTC VFS VFSTC Differential Nonlinearity Integral Nonlinearity Offset Error Offset Error Temperature Coefficient Full-Scale Voltage Full-Scale Voltage Temperature Coefficient Positive Supply Voltage Supply Current Short-Circuit Current Low Short-Circuit Current High Output Impedance to GND Output Line Regulation For Specified Performance (Note 4) VOUT Shorted to GND VOUT Shorted to VCC Input Code = 0 Input Code = 4095. VCC = 4.5V to 5.5V, VREF = 4.096V
q q q q
PARAMETER
CONDITIONS
MIN 12 12
TYP
MAX
UNITS Bits Bits
VREF VCC - 0.1V (Note 1) VREF VCC - 0.1V (Note 1), TA = 25C VREF VCC - 0.1V (Note 1) Measured at Code 20, TA = 25C Measured at Code 20
q q q
0.2
0.5 5.0 5.5 10 15
15 VREF = 4.096V, TA = 25C VREF = 4.096V 4.070 4.060 4.095 4.095 10 4.120 4.130
V/C V V ppm/C
q
Power Supply VCC ICC 2.7 450 55 65 30 0.2 5.5 700 120 120 120 1.5 V A mA mA LSB/V
Op Amp DC Performance
q q q q
2
U
LSB LSB LSB mV mV
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WW
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LTC1448
ELECTRICAL CHARACTERISTICS
VCC = 2.7V to 5.5V, VOUT A and VOUT B unloaded, REF VCC, TA = TMIN to TMAX, unless otherwise noted.
SYMBOL PARAMETER Voltage Output Slew Rate Voltage Output Settling Time Digital Feedthrough Reference Input RIN REF Digital I/O VIH VIL ILEAK CIN t1 t2 t3 t4 t5 t6 t7 t8 t1 t2 t3 t4 t5 t6 t7 t8 Digital Input High Voltage Digital Input Low Voltage Digital Input Leakage Digital Input Capacitance DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK CLK Low to CS/LD Low DIN Valid to CLK Setup DIN Valid to CLK Hold CLK High Time CLK Low Time CS/LD Pulse Width LSB CLK to CS/LD CS/LD Low to CLK CLK Low to CS/LD Low (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) (Note 6) VCC = 5V VCC = 3V VCC = 5V VCC = 3V VIN = GND to VCC (Note 6)
q q q q q q
CONDITIONS
q
MIN 0.5
TYP 1.0 14 0.3
MAX
UNITS V/s s nV * s
AC Performance (Notes 2, 3) to 0.5LSB
REF Input Resistance REF Input Range (Notes 5, 6)
q q
7.5 0 2.4 2.0
12.5
18 VCC
k V V V
0.8 0.6 10 10 40 0 40 40 50 40 20 20 60 0 60 60 80 60 30 30
V V A pF ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
Switching (VCC = 4.5V to 5.5V)
q q q q q q q q
Switching (VCC = 2.7V to 5.5V)
q q q q q q q q
The q denotes specifications which apply over the full operating temperature range. Note 1: Nonlinearity is defined from code 20 to code 4095 (full scale). See Applications Information. Note 2: Load is 5k in parallel with 100pF. Note 3: DAC switched between all 1s and the code corresponding to VOS for the part.
Note 4: Digital inputs at 0V or VCC. Note 5: VOUT can only swing from (GND + VOS) to (VCC - VOS) when output is unloaded. Note 6. Guaranteed by design, not subject to test.
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LTC1448 TYPICAL PERFORMANCE CHARACTERISTICS
Integral Nonlinearity (INL)
5 4 3
INL ERROR (LSB)
DNL ERROR (LSB)
2 1 0 -1 -2 -3 -4 -5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1448 G01
VCC - VOUT (V)
Minimum Output Voltage vs Output Sink Current
800
OUTPUT PULL-DOWN VOLTAGE (mV)
CODE: ALL 0's 700
SUPPLY CURRENT (mA)
600 125C 500 400 300 -55C 200 100 0 25C
0
5 10 OUTPUT SINK CURRENT (mA)
PIN FUNCTIONS
CLK (Pin 1): Serial Interface Clock. Internal Schmitt trigger on this input allows direct optocoupler interface. DIN (Pin 2): Serial Interface Data. Data on the DIN pin is latched into the shift register on the rising edge of the serial clock. CS/LD (Pin 3): Serial Interface Enable and Load Control. When CS/LD is low the CLK signal is enabled, so the data can be clocked in. When CS/LD is pulled high, data is loaded from the shift register into the DAC register, updating the DAC output and the CLK is disabled internally. REF (Pin 4): Reference Input for Both DACs. This pin can be tied to VCC. The output will swing from 0V to REF. The typical input resistance is 12.5k. VOUT A, VOUT B (Pins 5, 8): Buffered DAC Outputs. GND (Pin 6): Ground. VCC (Pin 7): Positive Supply Input. 2.7V VCC 5.5V. Requires a bypass capacitor to ground.
4
UW
Differential Nonlinearity (DNL)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -0.2 -0.3 -0.4 -0.5 0 512 1024 1536 2048 2560 3072 3584 4095 CODE
1448 TA02
Minimum Supply Headroom for Full Output Swing vs Load Current
0.8 0.7 0.6 0.5 0.4 0.3 0.2 0.1 0 0 5 10 LOAD CURRENT (mA) 15
1448 G03
VOUT < 1LSB CODE: ALL 1's VOUT = 4.095V
Supply Current vs Logic Input Voltage
2.0 1.6 1.2 0.8 0.4 0
15
1448 G04
0
1
3 4 2 LOGIC INPUT VOLTAGE (V)
5
1448 G06
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LTC1448
BLOCK DIAGRA W
LD CLK 1 DAC B REGISTER 12-BIT DAC B
+
8 VOUT B
-
DIN 2 24-BIT SHIFT REGISTER LD CS/LD 3 REF 4 DAC A REGISTER 12-BIT DAC A 7
VCC
6
GND
+
5 VOUT A
-
POWER-ON RESET
1448 BD
TI I G DIAGRA S
OPERATING SEQUENCE
DAC A INPUT MSB DIN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB MSB D0 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 DAC B INPUT LSB D0
CLK
1
2
3
4
CS/LD (ENABLE CLOCK) (UPDATE DAC OUTPUT)
1448 TD01
CLK
t8 B0-B PREVIOUS WORD B11-A MSB B0-A LSB B11-B MSB B0-B LSB t5 CS/LD
1448 TD02
DIN
W
5
UW
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
t4
t3
t1 t2 t6 t7
5
LTC1448
DEFI ITIO S
Differential Nonlinearity (DNL): The differerence between the measured change and the ideal 1LSB change for any two adjacent codes. The DNL error between any two codes is calculated as follows: DNL = (VOUT - LSB)/LSB where VOUT is the measured voltage difference between two adjacent codes. Digital Feedthrough: The glitch that appears at the analog output caused by AC coupling from the digital inputs when they change state. The area of the glitch is specified in (nV)(sec). Full-Scale Error (FSE): The deviation of the actual fullscale voltage from ideal. FSE includes the effects of offset and gain errors (see Applications Information). Integral Nonlinearity (INL): The deviation from a straight line passing through the endpoints of the DAC transfer curve (Endpoint INL). Because the output cannot go below zero, the linearity is measured between full scale and the lowest code which guarantees the output will be greater than zero. The INL error at a given input code is calculated as follows: INL = [VOUT - VOS - (VFS - VOS)(code/4095)]/LSB where VOUT is the output voltage of the DAC measured at the given input code. Least Significant Bit (LSB): The ideal voltage difference between two successive codes. LSB = VREF/4096 Resolution (n): Defines the number of DAC output states (2n) that divide the full-scale range. Resolution does not imply linearity. Voltage Offset Error (VOS): Nominally, the voltage at the output when the DAC is loaded with all zeros. A single supply DAC can have a true negative offset, but the output cannot go below zero (see Applications Information). For this reason, single supply DAC offset is measured at the lowest code that guarantees the output will be greater than zero.
OPERATIO
Serial Interface
The data on the DIN input is loaded into the shift register on the rising edge of the clock. Data is loaded as one 24bit word where the first 12 bits are for DAC A and the second 12 are for DAC B. For each 12-bit segment the MSB is loaded first. Data from the shift register is loaded into the DAC register when CS/LD is pulled high. The clock is disabled internally when CS/LD is high. Note: CLK must be low before CS/LD is pulled low to avoid an extra internal clock pulse. Voltage Output The LTC1448's rail-to-rail buffered outputs can source or sink 5mA over the entire operating temperature range
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while pulling to within 300mV of the positive supply voltage or ground. The output swings to within a few millivolts of either supply rail when unloaded and has an equivalent output resistance of 30 when driving a load to the rails. The output can drive 1000pF without going into oscillation. The output swings from 0V to the voltage at the REF pin, i.e., there is a gain of 1 from the REF to VOUT. Please note if REF is tied to VCC the output can only swing to (VCC - VOS). See Applications Information.
LTC1448
APPLICATIONS INFORMATION
Rail-to-Rail Output Considerations In any rail-to-rail DAC, the output swing is limited to voltages within the supply range. If the DAC offset is negative, the output for the lowest codes limits at 0V as shown in Figure 1b. Similarly, limiting can occur near full scale when the REF pin is tied to VCC. If VREF = VCC and the DAC full-scale error (FSE) is positive, the output for the highest codes limits at VCC as shown in Figure 1c. No full-scale limiting can occur if VREF is less than VCC - FSE. Offset and linearity are defined and tested over the region of the DAC transfer function where no output limiting can occur.
OUTPUT VOLTAGE
0
OUTPUT VOLTAGE
0V NEGATIVE OFFSET INPUT CODE (b)
1448 F01
Figure 1. Effects of Rail-to-Rail Operation on a DAC Transfer Curve: (a) Overall Transfer Function, (b) Effect of Negative Offset for Codes Near Zero Scale, (c) Effect of Positive Full-Scale Error for Input Codes Near Full Scale When VREF = VCC
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W
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VREF = VCC
POSITIVE FSE
OUTPUT VOLTAGE
INPUT CODE (c) VREF = VCC
2048 INPUT CODE (a)
4095
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LTC1448
TYPICAL APPLICATIONS
This circuit shows how to use one LTC1448 to make an autoranging ADC. The microprocessor sets the reference span and the Common pin for the analog input by loading the appropriate digital code into the LTC1448. VOUT A controls the Common pin for the analog inputs to the LTC1296 and VOUT B controls the reference span by setting the REF + pin on the LTC1296. The LTC1296 has a Shutdown pin that goes low in shutdown mode. This will turn off the PNP transistor supplying power to the LTC1448. The resistor and capacitor on the LTC1448 outputs act as a lowpass filter for noise.
P
8
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An Autoranging 8-Channel ADC with Shutdown
22F
+
5V VCC CS DOUT CLK DIN LTC1296 CH7 COM SSO REF + REF - CH0 8 ANALOG INPUT CHANNELS 74HC04 50k 50k 5V 0.1F 100 0.1F DIN CS/LD VCC LTC1448 GND 100 REF VOUT A 0.1F
1448 TA04
CLK
VOUT B
LTC1448
TYPICAL APPLICATIONS
CLK P DIN CS/LD
VOUT B PIN NOT SHOWN FOR CLARITY
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Digitally Programmable Current Source
5V VS + 6V TO 100V FOR RL 50
0.1F
VCC
REF VOUT A
RL
IOUT =
DIN * 5 0mA TO 10mA 4096 * RA
LTC1448 GND
+
LT1077 Q1 2N3440
-
RA 510 5%
1448 TA05
9
LTC1448
PACKAGE DESCRIPTION U
Dimensions in inches (millimeters) unless otherwise noted.
N8 Package 8-Lead PDIP (Narrow 0.300)
(LTC DWG # 05-08-1510)
0.400* (10.160) MAX 8 7 6 5
0.255 0.015* (6.477 0.381)
1 0.300 - 0.325 (7.620 - 8.255)
2
3
4 0.130 0.005 (3.302 0.127)
0.045 - 0.065 (1.143 - 1.651)
0.009 - 0.015 (0.229 - 0.381)
0.065 (1.651) TYP 0.125 (3.175) 0.020 MIN (0.508) MIN 0.018 0.003 (0.457 0.076) N8 1197
(
+0.035 0.325 -0.015 8.255 +0.889 -0.381
)
0.100 0.010 (2.540 0.254)
*THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED 0.010 INCH (0.254mm)
10
LTC1448
PACKAGE DESCRIPTION
0.010 - 0.020 x 45 (0.254 - 0.508) 0.008 - 0.010 (0.203 - 0.254) 0- 8 TYP
0.016 - 0.050 0.406 - 1.270
*DIMENSION DOES NOT INCLUDE MOLD FLASH. MOLD FLASH SHALL NOT EXCEED 0.006" (0.152mm) PER SIDE **DIMENSION DOES NOT INCLUDE INTERLEAD FLASH. INTERLEAD FLASH SHALL NOT EXCEED 0.010" (0.254mm) PER SIDE
Information furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
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Dimensions in inches (millimeters) unless otherwise noted.
S8 Package 8-Lead Plastic Small Outline (Narrow 0.150)
(LTC DWG # 05-08-1610)
0.189 - 0.197* (4.801 - 5.004) 8 7 6 5
0.228 - 0.244 (5.791 - 6.197)
0.150 - 0.157** (3.810 - 3.988)
1 0.053 - 0.069 (1.346 - 1.752)
2
3
4
0.004 - 0.010 (0.101 - 0.254)
0.014 - 0.019 (0.355 - 0.483)
0.050 (1.270) TYP
SO8 0996
11
LTC1448
TYPICAL APPLICATION
12-Bit, 3V to 5V Supply, Dual Voltage Output DAC
RELATED PARTS
PART NUMBER LTC1257 LTC1446/LTC1446L LTC1450/LTC1450L LTC1451 LTC1452 LTC1453 LTC1454/LTC1454L LTC1456 LTC1458/LTC1458L LTC1659 DESCRIPTION Single 12-Bit VOUT DAC, Full Scale: 2.048V, VCC: 4.75V to 15.75V, Reference Can Be Overdriven Up to 12V, i.e., FSMAX = 12V Dual 12-Bit VOUT DACs in SO-8 Package with Internal Reference Single 12-Bit VOUT DACs with Parallel Interface Single Rail-to-Rail 12-Bit DAC, Full Scale: 4.095V, VCC: 4.5V to 5.5V, Internal 2.048V Reference Brought Out to Pin Single Rail-to-Rail 12-Bit VOUT Multiplying DAC, VCC: 2.7V to 5.5V Single Rail-to-Rail 12-Bit VOUT DAC, Full Scale: 2.5V, VCC: 2.7V to 5.5V Dual 12-Bit VOUT DACs in SO-16 Package with Added Functionality Single Rail-to-Rail Output 12-Bit DAC with Clear Pin, Full Scale: 4.095V, VCC: 4.5V to 5.5V Quad 12 Bit Rail-to-Rail Output DACs with Added Functionality Single Rail-to-Rail 12-Bit VOUT DAC in MSOP-8 Package, VCC: 2.7V to 5.5V COMMENTS 5V to 15V Single Supply, Complete VOUT DAC in SO-8 Package LTC1446: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1446L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V LTC1450: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1450L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V 5V Low Power, Complete VOUT DAC in SO-8 Package Low Power, Multiplying VOUT DAC with Rail-to-Rail Buffer Amplifier in SO-8 Package 3V, Low Power, Complete VOUT DAC in SO-8 Package LTC1454: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1454L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power, Complete VOUT DAC in SO-8 Package with Clear Pin LTC1458: VCC = 4.5V to 5.5V, VOUT = 0V to 4.095V LTC1458L: VCC = 2.7V to 5.5V, VOUT = 0V to 2.5V Low Power Multiplying VOUT DAC in MSOP-8 Package. Output Swings from GND to REF. REF Input Can Be Tied to VCC
12
Linear Technology Corporation
1630 McCarthy Blvd., Milpitas, CA 95035-7417q (408)432-1900 FAX: (408) 434-0507q TELEX: 499-3977 q www.linear-tech.com
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2.7V TO 5.5V
0.1F DIN VCC P CLK CS/LD LTC1448 VOUT B GND OUTPUT B 0V TO REF
1448 TA03
REF VOUT A OUTPUT A 0V TO REF
1448f LT/TP 0398 4K * PRINTED IN USA
(c) LINEAR TECHNOLOGY CORPORATION 1997

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